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The D-PHY provides a synchronous link between a Master and Slave.
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A typical configuration includes:
- 1 Clock Lane (always unidirectional, Master → Slave)
- 1 or more Data Lanes (can be unidirectional or bi-directional depending on configuration)
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In half-duplex mode:
- Reverse-direction bandwidth is one-quarter of the forward direction.
- Token passing manages which side controls communication.
Signaling Modes
| Mode | Purpose | Characteristics |
|---|---|---|
| High-Speed (HS) | Fast data transfer | Differential, terminated signaling; data sent in bursts |
| Low-Power (LP) | Control signaling | Single-ended, non-terminated; low EMI design |
| Low-Power Escape Mode (optional) | Low-speed asynchronous data | Used only when needed |
| Alternate Low-Power Mode (ALP) (optional) | Uses differential signaling for LP functions | Suitable for long channels / IoT applications |
- A PHY must support LP mode, and may optionally support ALP mode and dynamic switching between LP and ALP (future-defined).
Lane Configuration
- Each Data Lane uses 2 wires, and the Clock Lane uses 2 wires → Minimum = 4 wires.
- HS mode: differential, terminated on both ends.
- LP mode: single-ended, non-terminated.
- ALP mode: differential, primarily terminated, but allows some special non-terminated events.
Data Rates
- Maximum HS rate depends on actual hardware implementation.
- Targeted performance ranges:
- 80–1500 Mbps per lane (no deskew)
- Up to 2500 Mbps (with deskew calibration)
- Up to 4500 Mbps (with equalization)
- Reverse HS (if used) may operate at lower data rates due to asymmetric architecture.
- Minimum ALP data rates:
- Forward: 4 Mbps
- Reverse: 1 Mbps
- Low-Power mode max rate: 10 Mbps
- Increasing Data Lanes → increases throughput.
- Burst mode can reduce effective throughput.
Required Capabilities at Higher Speeds
| Data Rate Capability | Required Feature |
|---|---|
| > 1500 Mbps | Deskew |
| > 2500 Mbps | Equalization + Spread Spectrum Clocking (SSC) |